LEVEL TRANSLATOR CIRCUIT WITH IMPROVED LEVEL EFFICIENCY AND TRANSLATION CAPACITY IN TWO DOMINES, IN PARTICULARLY FOR USE IN A MEMORY DEVICE

摘要

A level shifter circuit (1), to shift an input signal (LV_IN), switching within a first voltage range, to generate at least a first output signal (HV_OUT), correspondingly switching within a second voltage range, higher than the first voltage range, having: a latching core (10) with latching input and output terminals (L_IN, L_OUT) and having a supply line (LS_TOP) designed to be supplied by a supply voltage (V) and a reference line (LS_BOT) designed to be coupled to a reference voltage (SHIFTED_GND); capacitive-coupling elements (13a-13b) coupled to the latching input and output terminals of the latching core (10); a driving stage (16) to bias the capacitive-coupling elements (13a-13b) with biasing signals (CP1_BOT-CP4_BOT) generated based on the input signal (LV_IN); and a decoupling stage (14, 15), driven by the driving stage (16) through the capacitive-coupling elements (13a-13b), to decouple the supply line (LS_TOP) from the supply voltage (V) and the reference line (LS_BOT) from the reference voltage (SHIFTED_GND) during switching of the input signal.