首页> 外国专利> Voltage level translator for translating low to high voltage levels in digital integrated circuits

Voltage level translator for translating low to high voltage levels in digital integrated circuits

机译:电压电平转换器,用于将数字集成电路中的低电压电平转换为高电压电平

摘要

An improved low voltage to high voltage translator for digital electronic circuits providing reduced rise times, fall times and transition times that remain independent of operating conditions. This is accomplished by modifying a conventional low-to-high voltage translator to include a switched active pull-up at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the output from the low-to-high-voltage translator and a switched active pull-down at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the complement of the output from the low-to-high-voltage translator, so as at to provide regenerative pull-up and pull-down that also counteracts the bootstrap capacitance at the output of the first high-voltage switch.
机译:用于数字电子电路的改进的低压到高压转换器,提供了减少的上升时间,下降时间和过渡时间,而与工作条件无关。这是通过修改常规的低压至高压转换器来实现的,以在第一高压开关的输出端包括一个开关有源上拉电阻,该有源上拉电阻由输入低压信号控制并由低压输出端选通到高压转换器,并且在第一高压开关的输出处有一个开关的有源下拉,由输入低压信号控制,并由低压到高压转换器的输出的互补来选通,以提供再生上拉和下拉,这也抵消了第一高压开关输出处的自举电容。

著录项

  • 公开/公告号US2004124879A1

    专利类型

  • 公开/公告日2004-07-01

    原文格式PDF

  • 申请/专利权人 NARWAL RAJESH;

    申请/专利号US20030675923

  • 发明设计人 RAJESH NARWAL;

    申请日2003-09-29

  • 分类号H03K19/0175;

  • 国家 US

  • 入库时间 2022-08-21 23:20:00

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