Computer-implemented method and computing system for designing integrated circuit by considering process variations of wire

摘要

This disclosure discloses a computer implemented method and a computing system for the design of integrated circuits. A method of designing an integrated circuit according to the teachings of the present disclosure includes receiving layout data for an integrated circuit and a technology file including parasitic component corners of each of a plurality of layers included in the integrated circuit, The parasitic component extraction operation is performed on the corners of the parasitic component of the layer included in the arc, thereby generating parasitic component data including delay variation data of the timing arc, and performing timing analysis on the integrated circuit based on the parasitic component data Thereby generating timing analysis data.