Method for manufacturing void spacers for N7 / N5 FINFET and more

摘要

Embodiments disclosed herein relate to improved transistors having reduced parasitic capacitance. In one embodiment, the transistor device has a three-dimensional fin structure that protrudes from the surface of the substrate-the three-dimensional fin structure includes a top surface and two opposed sidewalls-on two opposing sidewalls of the three- A sacrificial spacer layer formed conformally on the first insulating layer, the sacrificial spacer layer comprising a material based on aluminum oxide or a material based on titanium nitride, and a second insulating layer formed conformally on the sacrificial spacer layer, Insulating layer.