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RPC APPARATUS AND METHOD FOR A REDUCED PIN COUNTRPC MEMORY BUS INTERFACE INCLUDING A READ DATA STROBE SIGNAL

机译:用于减少的PIN数的RPC设备和方法包括读取数据选通信号的RPC存储器总线接口

摘要

Disclosed are an apparatus for a reduced pin count (RPC) memory bus interface including a read data strobe signal and a method thereof. The interface includes a chip selection for transmitting a chip selection signal indicating when a peripheral device is activated, wherein the bus interface provides communication between a host device and the peripheral device. The interface also includes differential clock pairs for carrying differential clock signals. A read data strobes is included in the interface for transmitting the read data strobe signals from the peripheral device. The interface includes a data bus for carrying commands, addressers, and data information. The read data strobe indicates when valid data is present on the data bus.
机译:公开了一种用于减少引脚数(RPC)存储器总线接口的设备,该设备包括读取数据选通信号及其方法。该接口包括芯片选择,该芯片选择用于发送指示何时激活外围设备的芯片选择信号,其中总线接口提供主机设备与外围设备之间的通信。该接口还包括用于传输差分时钟信号的差分时钟对。接口中包括读取数据选通信号,用于从外围设备传输读取数据选通信号。该接口包括用于承载命令,寻址器和数据信息的数据总线。读数据选通指示何时在数据总线上存在有效数据。

著录项

  • 公开/公告号KR20190116212A

    专利类型

  • 公开/公告日2019-10-14

    原文格式PDF

  • 申请/专利权人 CYPRESS SEMICONDUCTOR CORPORATION;

    申请/专利号KR20190121705

  • 发明设计人 ZITLAW CLIFFORD ALAN;

    申请日2019-10-01

  • 分类号G06F13/42;G06F1/08;G06F1/10;G06F13/28;G06F13/40;

  • 国家 KR

  • 入库时间 2022-08-21 11:49:36

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