FIELD: calculating; counting.;SUBSTANCE: invention relates to the computer equipment. Device comprises generator of m-sequence of length (GML) over GF(pm) of length pn-1, where n = 2m, (pm-l)≡0 (mod 4), with arithmetic in GF(pm), conversion unit (CU) of output symbol of m-sequence in the form of m -p-ary coefficients in ⎡m (log2p)⎤-bit binary number, binary outputs of which are connected to corresponding address inputs of ROM with volume pm×1 bit. GML over GF (pm) of length pn-1 is implemented in the form of serially connected m-sequence generator over GF(p) of length pn-1, consisting of n-bit shift register of p-ary numbers, which output bits are connected to inputs of scalar multiplication unit (SMU), at that output of SMU is connected to input of shift register, and unit for multiplication by matrix (UMM) of p-ary numbers of order n×m, first column of which corresponds to zero shift and is equal to (1 0 0…0)T, respectively, i-column of said matrix corresponds to m-sequence shift by (i-1) (pm+1), 1 = 2,…,m, wherein n UMM inputs are connected to corresponding shift register bits outputs, and m UMM outputs are connected to binary m-bit p-to-binary CU m inputs, wherein series-connected zero and unit decimator are introduced, as well as a two-input OR element connected at the first input to the decimator output of units, and at the second input - to the ROM output, wherein the input of the zero decoder is connected to the output of the CU.;EFFECT: technical result consists in improvement of high-speed generator of pseudorandom binary sequences of complex structure.;1 cl, 3 dwg, 1 tbl
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机译:领域:计算;计数:本发明涉及计算机设备。该设备包括长度为p n Sup> -1的GF(p m Sup>)上的长度为m的序列(GML)的生成器,其中n = 2m,(p m Sup> -l)≡0(mod 4),在GF(p m Sup>)中进行算术运算,以m -p-的形式表示m序列的输出符号的转换单位(CU)二进制系数,以 2 Sub> p)⎤位二进制数表示,其二进制输出连接到容量为p m Sup>×1位的ROM的相应地址输入。长度为p n Sup> -1的GF(p m Sup>)上的GML以串联连接的长度为p 的GF(p)的m序列发生器的形式实现n Sup> -1,由p元数的n位移位寄存器组成,其输出位连接到标量乘法单元(SMU)的输入,在SMU的输出处连接到移位寄存器的输入,并且i×n阶p元数的矩阵乘以(UMM)的单位,其第一列对应于零位移,分别等于(1 0 0…0) T Sup>,i所述矩阵的列对应于m序列移位(i-1)(p m Sup> +1),1 = 2,…,m,其中n个UMM输入连接到相应的移位寄存器位输出和m个UMM输出连接到二进制m位p-to-binary CU m个输入,其中引入了串联的零和单位抽取器,以及一个在第一个输入处连接到抽取器的双输入OR元件单元的输出,并在第二个输入-到ROM输出,其中零解码器的输入连接到CU的输出。效果:技术成果在于改进了具有复杂结构的伪随机二进制序列的高速生成器。1cl,3 dwg,1 tbl
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