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Small multiplier after initial approximation for operations with increasing precision

机译:初始近似后的较小乘数,用于提高精度的运算

摘要

In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.
机译:在一方面,处理器包括用于迭代细化方法(例如,Newton-Raphson)以评估诸如平方根,倒数之类的函数以及用于除法的电路。该电路包括用于产生初始近似的电路。其中可以包含查阅表(LUT)。 LUT可以产生输出(具有与实现相关的处理),该输出形成具有多个精度位的值的初始近似值。有限精度乘法器将该初始近似值与另一个值相乘;有限精度乘法器的输出将进入全精度乘法器电路,该电路将在实施的特定优化过程中执行迭代所需的其余乘法。例如,在除法中,要计算的输出是除数的倒数。全精度乘法器电路需要第一数量的时钟周期才能完成,而小型乘法器和初始逼近电路都需要在第一数量的时钟周期内完成。

著录项

  • 公开/公告号GB2532332B

    专利类型

  • 公开/公告日2019-05-22

    原文格式PDF

  • 申请/专利权人 IMAGINATION TECHNOLOGIES LIMITED;

    申请/专利号GB20150017020

  • 发明设计人 LEONARD RARICK;

    申请日2015-09-25

  • 分类号G06F7/487;G06F7/535;G06F7/552;

  • 国家 GB

  • 入库时间 2022-08-21 11:43:20

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