WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION

摘要

A wafer-level package includes a plurality of dies (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1502, 1504_1-1504_2, 1602, 1604_1-1604_4) and a plurality of connection paths. The dies include at least a first die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4) and a second die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4). The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output pads arranged on the first side of the first die to input/output pads arranged on the first side of the second die, wherein adjacent input/output pads on the first side of the first die are connected to adjacent input/output pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out package or a chip on wafer on substrate package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.