LEVEL SHIFTER CIRCUIT WITH TRANSISTOR DRIVE STRENGTH VARIATION COMPENSATION

摘要

A level shifter circuit (101) is described herein for shifting a signal from a first voltage domain (Vdd1) to a second voltage domain (Vdd2). The level shifter circuit includes two current paths (113, 115) between a supply terminal of the first voltage domain (Vss1) and a supply terminal of the second voltage domain (Vdd2). The first and second current paths each include a differential transistor (155, 157) that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal (INPUT) to be translated to the second voltage domain. The level shifter includes a latch circuit (107) in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage (CBV) for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.