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Semiconductor devices having through-stack interconnects for facilitating connectivity testing

机译:具有贯穿式互连的半导体器件,用于促进连通性测试

摘要

Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
机译:本文公开了具有用于促进连通性测试的叠层互连的半导体器件以及相关联的系统和方法。在一个实施例中,一种半导体器件包括半导体管芯的堆叠和延伸穿过该堆叠以电耦合半导体管芯的多个贯穿堆叠互连。互连包括功能互连和至少一个测试互连。与功能互连相比,测试互连位于堆栈的一部分中,更容易出现连接缺陷。因此,测试测试互连的连通性可以提供功能互连的连通性的指示。

著录项

  • 公开/公告号US10692841B2

    专利类型

  • 公开/公告日2020-06-23

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US201816020140

  • 发明设计人 CHRISTIAN N. MOHR;SCOTT E. SMITH;

    申请日2018-06-27

  • 分类号H01L21/66;G01R31/26;H01L25/065;G01R27/14;H01L23/538;

  • 国家 US

  • 入库时间 2022-08-21 11:31:05

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