首页> 外国专利> Dynamic bit-line clamping circuit for computing-in-memory applications and clamping method thereof

Dynamic bit-line clamping circuit for computing-in-memory applications and clamping method thereof

机译:用于内存计算应用的动态位线钳位电路及其钳位方法

摘要

A dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal and includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage and includes a switch. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.
机译:一种用于内存计算应用的动态位线钳位电路,用于通过至少一个参考信号钳位位线,并包括钳位节点,第一钳位单元,第二钳位单元,第一反馈控制单元和第二反馈控制单元。第一钳位单元电连接在位线和钳位节点之间。第二钳位单元电连接在钳位节点和电源电压之间并且包括开关。第二反馈控制单元电连接到钳位节点和开关。第二反馈控制单元根据至少一个参考信号和钳位节点的电压电平产生开关信号。所述开关通过所述切换信号进行切换,以根据所述至少一个参考信号来钳位所述钳位节点的电压电平。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号