Chip design method of optimizing circuit performance according to change in PVT operation conditions

摘要

A method of designing a chip having an integrated circuit is provided. The method includes obtaining delta cell delays and delta net delays according to a process, voltage, and temperature (PVT) corner change with respect to a plurality of cells and a plurality of nets forming the integrated circuit; analyzing sensitivity with respect to a delay according to the PVT corner change of a plurality of paths in the integrated circuit, by using the delta cell delays and the delta net delays; determining N-number of sensitivity-critical paths among the plurality of paths based on a result of the analysis, wherein N is an integer greater than or equal to 0; and performing an engineering change order (ECO) based on a result of the determination.