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Tunnel field-effect transistor with reduced trap-assisted tunneling leakage
Tunnel field-effect transistor with reduced trap-assisted tunneling leakage
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机译:减少陷阱辅助隧穿泄漏的隧道场效应晶体管
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摘要
The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
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