Scalable graphene nanoribbon arrays for digital transistors

摘要

Methods for fabricating a graphene nanoribbon array in accordance with several embodiments of the present invention can include the steps of depositing PMMA dots on a substrate in an m×n grid, to selectively seed graphene flakes on the substrate by controlling the growth of the graphene flakes on the substrate during the graphene deposition. The methods can further include the steps of masking the graphene flake edges with an insulator layer, at a very low deposition time or at a lower precursor concentration, to ensure there are not enough insulator molecules to form a complete layer over the flakes, but only enough insulator to form around the flakes edges. Once the graphene flake edges are masked, the bulk graphene can be etched, and the masking insulator can be removed to expose the resulting graphene nanoribbon.