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Timing analysis for electronic design automation of parallel multi-state driver circuits
Timing analysis for electronic design automation of parallel multi-state driver circuits
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机译:并行多状态驱动器电路电子设计自动化的时序分析
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摘要
A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.
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