DIFFERENT GATE WIDTHS FOR UPPER AND LOWER TRANSISTORS IN A STACKED VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR STRUCTURE

摘要

A method of forming a semiconductor structure includes forming vertical fins comprising a first semiconductor layer, an isolation layer and a second semiconductor layer, the first and second semiconductor layers providing vertical transport channels for lower and upper vertical transport field-effect transistors (VTFETs) of a stacked VTFET structure. The method also includes forming a first gate stack for the lower VTFET surrounding a first portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack for the upper VTFET surrounding a second portion of the second semiconductor layer of the vertical fins. The first and second portions have different sizes such that the upper and lower VTFETs of the stacked VTFET structure have different effective gate widths.