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Central arbitration scheme for a highly efficient interconnection topology in a GPU
Central arbitration scheme for a highly efficient interconnection topology in a GPU
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机译:用于GPU中高效互连拓扑的中央仲裁方案
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摘要
According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.
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