首页> 外国专利> MAPPING SOFTWARE CONSTRUCTS TO SYNCHRONOUS DIGITAL CIRCUITS THAT DO NOT DEADLOCK

MAPPING SOFTWARE CONSTRUCTS TO SYNCHRONOUS DIGITAL CIRCUITS THAT DO NOT DEADLOCK

机译:映射软件构造为同步的数字电路,但不会解除锁定

摘要

A disclosed language includes a loop construct that maps to a circuit implementation. The circuit implementation may be used to design or program a synchronous digital circuit. The circuit implementation includes a hardware pipeline that implements the loop's body and condition. The circuit implementation also includes hardware first-in-first-out queues that marshal threads (i.e. collections of local variables) into, around, and out of the pipeline. A pipeline policy circuit limits the number of threads allowed within the pipeline to the capacity of the queue.
机译:公开的语言包括映射到电路实现的循环构造。电路实现可用于设计或编程同步数字电路。电路实现包括实现循环主体和条件的硬件管线。电路实现还包括硬件先进先出队列,该队列将线程(即局部变量的集合)编组到管道中,管道中和管道外。管道策略电路将管道内允许的线程数限制为队列的容量。

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