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MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE
MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE
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机译:使用错误检测改正码的存储器控制器和数据总线反转方法
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摘要
Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.
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