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RESETTING CLOCK DIVIDER CIRCUITRY PRIOR TO A CLOCK RESTART
RESETTING CLOCK DIVIDER CIRCUITRY PRIOR TO A CLOCK RESTART
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机译:在重新启动时钟之前重置时钟分频器电路
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摘要
A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.
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