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MEMORY ARRAYS WITH VERTICAL THIN FILM TRANSISTORS COUPLED BETWEEN DIGIT LINES
MEMORY ARRAYS WITH VERTICAL THIN FILM TRANSISTORS COUPLED BETWEEN DIGIT LINES
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机译:带数字线的垂直薄膜晶体管的存储阵列
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摘要
In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.
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