This invention relates to the field of computer engineering and microelectronics and can be used for building hardware control devices and digital devices operating in a residual class system. The computing device is intended for implementation of multiplication A∙B=R (mod 8). The device contains seven elements AND, two elements MODULO TWO ADDING, six inputs and three outputs. The complexity of the device (defined by the number of logical element inputs) is 22, and its speed of operation determined by the scheme depth is 2τ, where τ is a delay by one logical element. The device for modulo eight multiplication works as follows. The inputs of the device receive values of binary variables a1, b1, a2, b2, a3, b3, taking least, medium and higher values of bits of operands A and B, where A=a1+2a2+4a3 and B=b1+2b2+4b3. At the outputs of the device, logic functions R1, R2, R3, taking values of the least r1, medium r2 and higher r3 bits of the result of operation A∙B=R (mod 8) are realized, where R=r1+2r2+4r3.
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