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MODULO EIGTH MULTIPLICATION DEVICE

机译:MODULO EIGTH倍增装置

摘要

This invention relates to the field of computer engineering and microelectronics and can be used for building hardware control devices and digital devices operating in a residual class system. The computing device is intended for implementation of multiplication A∙B=R (mod 8). The device contains seven elements AND, two elements MODULO TWO ADDING, six inputs and three outputs. The complexity of the device (defined by the number of logical element inputs) is 22, and its speed of operation determined by the scheme depth is 2τ, where τ is a delay by one logical element. The device for modulo eight multiplication works as follows. The inputs of the device receive values of binary variables a1, b1, a2, b2, a3, b3, taking least, medium and higher values of bits of operands A and B, where A=a1+2a2+4a3 and B=b1+2b2+4b3. At the outputs of the device, logic functions R1, R2, R3, taking values of the least r1, medium r2 and higher r3 bits of the result of operation A∙B=R (mod 8) are realized, where R=r1+2r2+4r3.
机译:本发明涉及计算机工程和微电子学领域,并且可以用于构建在残差类系统中运行的硬件控制设备和数字设备。该计算设备旨在实现乘法A∙B = R(模数8)。该设备包含七个元素AND,两个元素MODULO TAD ADDD,六个输入和三个输出。设备的复杂度(由逻辑元素输入的数量定义)为22,其操作速度由方案深度确定为2τ,其中τ是一个逻辑元素的延迟。模八乘法的设备的工作原理如下。设备的输入接收二进制变量a 1 ,b 1 ,a 2 ,b 2 的值, a 3 ,b 3 ,分别取操作数A和B的位的最低,中值和较高值,其中A = a 1 + 2a < Sub> 2 + 4a 3 和B = b 1 + 2b 2 + 4b 3 。在设备的输出端,逻辑函数R 1 ,R 2 ,R 3 ,取r 1 < / Sub>,实现操作A∙B = R(mod 8)的结果的中等r 2 和更高的r 3 位,其中R = r 1 + 2r 2 + 4r 3

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