DEVICE FOR MULTIPLICATION OF ARBITRARY MODULO 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c02e00140011200000026060f001a00ffffffff000010000000c0ffffffa1ffffff00010000810100000b00000026060f000c004d61746854797065000050001c000000fb0220ff00000000000090010000000004020020417269616c000000a40f0a0c70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01000008000000320a8801d5000100000069791c000000fb02e0fe00000000000090010000000004020020417269616c000000e1040a7e70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01010004000000f001000008000000320a400133000100000061790a00000026060f000a00ffffffff0100000000001c000000fb021000070000000000bc02000000cc0102022253797374656d0048e50c664800000a0021008a01000000000000000088f21200040000002d01000004000000f0010100030000000000AND 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c

摘要

The invention relates to computer engineering and automatics and is intended for multiplication of arbitrary modulo EMBED Equation.3 and EMBED Equation.3 residues of residue number system. A device for multiplication of arbitrary modulo EMBED Equation.3 and EMBED Equation.3 residues of residue number system comprises first and second input registers, output register, first and second decoders, first and second groups of OR gates, each group containing EMBED Equation.3 OR gates, first and second groups of AND gates, each group containing EMBED Equation.3 AND gates, switch, modulo two adder, first, second, third and fourth OR gates, first and second AND gates. The device further comprises fifth and sixth OR gates, third and fourth group of AND gates, group of key elements, encoder, modulo EMBED Equation.3 adder. The technical result is in device enhancement due to execution of multiplication operator directly in binary code.