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COVERAGE BASED MICROELECTRONIC CIRCUIT, AND METHOD FOR PROVIDING A DESIGN OF A MICROELECTRONIC CIRCUIT

机译:基于覆盖率的微电子电路以及提供微电子电路设计的方法

摘要

Microelectronic circuit com- prisesaplurality of logic units and register circuits, arranged into a plu- rality of processing paths, and a plu- rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera- tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de- lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro- cessing paths comprise logic units be- longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.
机译:微电子电路包括逻辑单元和寄存器电路的复数个,排列成多个处理路径,多个监视单元分别与所述处理路径中的一个相关。每个所述监视单元被配置为产生观察信号,作为对相应处理路径的异常操作的响应。根据可能产生的延迟量,所述多个逻辑单元中的每个逻辑单元属于多个延迟类别之一。所述延迟类别包括第一,第二和第三类别,其中第一类别涵盖可能产生最长延迟的逻辑单元,第二类别涵盖可能产生比所述第一类别短的延迟的逻辑单元,并且第三类包括可能产生比所述第二类短的延迟的逻辑单元。所述多个处理路径中的至少一些包括属于所述第二类但没有监视单元的逻辑单元。所述多个处理路径中的至少一些包括属于所述第三类的逻辑单元,但是具有与它们关联的监视单元。

著录项

  • 公开/公告号WO2020109647A1

    专利类型

  • 公开/公告日2020-06-04

    原文格式PDF

  • 申请/专利权人 MINIMA PROCESSOR OY;

    申请/专利号WO2018FI50857

  • 发明设计人 GUPTA NAVNEET;

    申请日2018-11-27

  • 分类号G06F17/50;G06F11/07;H03K19/007;H03K19/003;H03K3/037;G06F1/3296;H03K19;G01R31/3181;

  • 国家 WO

  • 入库时间 2022-08-21 11:10:57

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