PARITY CHECK MATRIX GENERATING DEVICE OPERATING METHOD THEREOF AND ERROR CORRECTION CIRCUIT USING PARITY CHECK MATRIX GENERATED BY THE SAME

摘要

According to the present invention, a device for generating a low density parity check (LDPC) code parity check matrix including a non-binary cyclic permutation matrix comprises: a first memory for storing a first weight value that is position information in a parity check matrix of the non-binary cyclic permutation matrix; a second memory for storing a second weight value that is a cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory for storing a third weighting value for determining a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generation device configured to apply a non-binary value to the matrix elements of 1 of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix, and apply any one of the first to third weighting values to the non-binary value to generate the non-binary cyclic permutation matrix by reflecting any one or more of the first to third weight values in the non-binary value.