HIGH BANDWIDTH MEMORY RELIABILITY, ACCESSIBILITY, AND SERVICEABILITY (RAS) CACHE ARCHITECTURE

摘要

The present invention provides a high bandwidth memory (HBM) reliability, accessibility, and serviceability (RAS) cache architecture with increased reliability. According to one embodiment of the present invention, a device comprises a plurality of stacked integrated circuit (IC) dies including a memory cell die and a logic die. The memory cell die is formed to store data in a random access type based on a memory address. The logic die comprises: an interface connected to the stacked IC dies and configured to perform memory access communications between the memory cell die and at least one external device; and a reliability circuit reducing data errors in the memory cell die. The reliability circuit comprises a sub memory to store data in the random access type and an address table to map a memory address related to an error with a portion of the sub memory. When memory access to the stacked IC dies is generated, the reliability circuit determines whether the memory access is related to the error. When the memory access is related to the error, the reliability circuit uses the sub memory to complete the memory access.;COPYRIGHT KIPO 2020