MSR FPGA FPGA ACCELERATION SYSTEM FOR MSR CODES

摘要

According to a general aspect, a device may include a host interface circuit configured to receive an offload command from a host processing device, the offload command directing the device to calculate an error correction code associated with a plurality of data elements. The apparatus can include a memory interface circuit configured to receive a plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The device may include a plurality of error code calculation circuits configured to calculate the error correction code at least partially without further processing by the host processing device.