Chemical mechanical planarization (CMP) has become the enabling planarization technique of choice for current and emerging silicon integrated circuit (IC) fabrication processes. This work studies CMP in dielectric materials in particular, which is widely used in device formation for isolation and in interconnect formation for dielectric planarization. The physical understanding of the process is essential for CMP tool engineers to design optimal consumables, for circuit engineers to make the layout design manufacturing friendly and for process engineers to better control the process. The major contributions of this work are a framework to study the physics of CMP and physically-based particle-level and die-level models of polishing and planarization. A framework for studying the physics of CMP is established by analyzing the complex system and decoupling the interactions occurring at different scales. A particle- level CMP model is developed that bridges the microscopic polishing mechanisms to the macroscopic properties of the system. A physically-based die-level model is proposed by explicit modeling of the pad and pad surface asperities, with model parameters that are based on the physical properties of the pad rather than purely fitting parameters. A semi-empirical die-level CMP model, motivated by the new physically-based die-level model, is developed that improves upon previous pattern density step-height models by making realistic assumptions and approximations, and improving the ease of computation. The model is applied to simulate polishing of either single- material or dual-material structures with either conventional or non conventional slurries. The die-level models are then applied to engineering problems, including design for manufacturing, nanotopography impact, wafer edge roll-off effects, and motor current based endpoint detection.
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