Over the past few years, the Intel Fab-17 facility has aggressively pursued lean methodology to reduce the manufacturing costs associated with its aging 200mm diameter wafer process. One area ripe with improvement opportunities is the processes supplying and managing Test Wafers, which are non-production wafers used to verify production tools and operations. With four test wafer types, hundreds of different sequences of operations (defined as routes), and varying consumption trends, thousands of decisions must be made daily to ensure Test Wafers are available on time and with the proper base characteristics. To further illustrate the magnitude and importance of Test Wafer systems, roughly the same number of Test Wafers are introduced each time period into the fab as production wafers. Through direct observation and process mapping techniques, I identified two system level projects, each containing enormous cost and performance improvements to the entire facility. Project One: Reallocating excess inventory In analyzing the Test Wafer inventory quantity and consumption rates in primary stockroom, I noticed that certain routes had excess inventory while others were deficient, thus leading to significantly more expensive Test Wafers types to be used instead. In order to maximize realized cost savings, I developed a linear optimization program which distributed excess Test Wafer inventory to areas of need. Different re-allocation costs, initial material specifications, and forecasted consumption needs constrained the quantity and location for this redistribution.
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