As multi-processor computer systems become more prevalent in today's computer industry, it is clear that routers and interconnection networks are critical components of these multi-processor systems. Therefore, there is a need to obtain accurate area and power models for these critical components so that we can better understand the area and power tradeoffs as we balance the on-chip and off-chip communication energy given a fixed energy budget. In this thesis, we propose an alternative method to understanding the power and area tradeoffs for routers by not solely relying on analytical models, on which most current studies done on this topic are based. Instead, in this thesis we propose analyzing the area versus power tradeoff for these routers and interconnection networks using an Application Specific Integrated Circuit (ASIC) flow in a commercially available IBM 90nm process technology. This thesis shows that multiplexer routers are more area and power efficient compared to matrix routers since matrix routers quickly exhibit a quadratic-like increase in area and power as the number of ports and port width increases. In addition, we show that there is a real gain in area when the router is shared among 4 or more cores. The savings by sharing the same router among multiple cores does not continue indefinitely, since after a certain port number and port width size, the increase in the crossbar size can no longer be compensated by sharing the router. So for a fixed port-width, there is always a sweet spot for the number of ports where a local minimum can be found for the Router Area Overheard per Core.
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