Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits

摘要

Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing.