The construction of topological error correction codes requires the abilityto fabricate a lattice of physical qubits embedded on a manifold with anon-trivial topology such that the quantum information is encoded in the globaldegrees of freedom (i.e. the topology) of the manifold. However, themanufacturing of large-scale topological devices will undoubtedly suffer fromfabrication errors---permanent faulty components such as missing physicalqubits or failed entangling gates---introducing permanent defects into thetopology of the lattice and hence significantly reducing the distance of thecode and the quality of the encoded logical qubits. In this work we investigatehow fabrication errors affect the performance of topological codes, using thesurface code as the testbed. A known approach to mitigate defective latticesinvolves the use of primitive SWAP gates in a long sequence of syndromeextraction circuits. Instead, we show that in the presence of fabricationerrors the syndrome can be determined using the supercheck operator approachand the outcome of the defective gauge stabilizer generators without anyadditional computational overhead or the use of SWAP gates. We report numericalfault-tolerance thresholds in the presence of both qubit fabrication and gatefabrication errors using a circuit-based noise model and the minimum-weightperfect matching decoder. Our numerical analysis is most applicable to 2Dchip-based technologies, but the techniques presented here can be readilyextended to other topological architectures. We find that in the presence of 8%qubit fabrication errors, the surface code can still tolerate a computationalerror rate of up to 0.1%.
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