Linear power amplifiers used to implement the Ultra-Wideband standard must beudbacked off from optimum power efficiency to meet the standard specifications andudthe power efficiency suffers. The problem of low efficiency can be mitigated by polarudmodulation. Digital polar architectures have been employed on numerous wirelessudstandards like GSM, EDGE, and WLAN, where the fractional bandwidths achievedudare only about 1%, and the power levels achieved are often in the vicinity of 20 dBm.udCan the architecture be employed on wireless standards with low-power and highudfractional bandwidth requirements and yet achieve good power efficiency?udTo answer these question, this thesis studies the application of a digital polar transmitterudarchitecture with parallel amplifier stages for UWB. The concept of the digitaludtransmitter is motivated and inspired by three factors. First, unrelenting advancesudin the CMOS technology in deep-submicron process and the prevalence of low-costudDigital Signal processing have resulted in the realization of higher level of integrationudusing digitally intensive approaches. Furthermore, the architecture is an evolutionudof polar modulation, which is known for high power efficiency in other wireless applications.udFinally, the architecture is operated as a digital-to-analog converter whichudcircumvents the use of converters in conventional transmitters.udModeling and simulation of the system architecture is performed on the Agilent AdvancedudDesign System Ptolemy simulation platform. First, by studying the envelopeudsignal, we found that envelope clipping results in a reduction in the peak-to-averageudpower ratio which in turn improves the error vector magnitude performance (figureudof merit for the study). In addition, we have demonstrated that a resolution of threeudbits suffices for the digital polar transmitter when envelope clipping is performed.udNext, this thesis covers a theoretical derivation for the estimate of the error vectorudmagnitude based on the resolution, quantization and phase noise errors. An analysisudon the process variations - which result in gain and delay mismatches - for auddigital transmitter architecture with four bits ensues. The above studies allow RFuddesigners to estimate the number of bits required and the amount of distortion thatudcan be tolerated in the system.udNext, a study on the circuit implementation was conducted. A DPA that comprisesud7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7udcascode transistors (individually connected in series with the bottom amplifiers)uddigitally controlled by a 3-bit digitized envelope signal to reconstruct the UWBudsignal at the output. Through the use of NFET models from the IBM 130-nmudtechnology, our simulation reveals that our DPA is able to achieve an EVM of -ud22 dB. The DPA simulations have been performed at 3.432 GHz centre frequencyudwith a channel bandwidth of 528 MHz, which translates to a fractional bandwidthudof 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while deliveringud-1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power.udIn addition, we performed a yield analysis on the digital polar amplifier, basedudon unit-weighted and binary-weighted architecture, when gain variations are introducedudin all the individual stages. The dynamic element matching method is alsoudintroduced for the unit-weighted digital polar transmitter. Monte Carlo simulationsudreveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with audstandard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%,udwhile the yields of the unit-weighted architectures are in the neighbourhood of 95%.udMoreover, the dynamic element matching technique demonstrates an improvementudin the yield by approximately 3%.udFinally, a hardware implementation for this architecture based on software-definedudarbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polarudtransmitter under ideal combining conditions fulfill the European Computer ManufacturersudAssociation requirements. The proposed experimental setup, believed toudbe the first ever attempted, confirm the feasibility of a digital polar transmitter architectureudfor Ultra-Wideband. In addition, we propose a number of power combiningudtechniques suitable for the hardware implementation. Spatial power combining, inudparticular, shows a high potential for the digital polar transmitter architecture.udThe above studies demonstrate the feasibility of the digital polar architecture withudgood power efficiency for a wideband wireless standard with low-power and highudfractional bandwidth requirements.
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