In some cases, signal processing is easier in frequency-domain and Discrete Fourier Transform (DFT) is a useful tool to convert signals between time and frequency domains. Fast Fourier Transform (FFT) is an efficient algorithm for computing DFT. FFT has a number of applications, where frequency-domain of a signal needs to be analyzed. It gained attention in communication systems because FFT is a crucial processing operation in the Orthogonal Frequency Division Multiplexing (OFDM) systems. The research work carried out in this thesis presents hardware implementation of FFT processors. The processors’ architectures are designed based on Single-path Delay Feedback (SDF) FFT architecture scheme, which implements the radix-22 and identical radix-22 FFT algorithms for 2048-point FFT. The designed identical radix-22 FFT algorithm has similar number of non-trivial complex twiddle factor multiplication stages, identical to radix-22 FFT algorithm but less complex operations. The lower complexity makes it an area efficient, memory efficient, reduce the multiplication cost and power consumption. Moreover, the computational complexity of the FFT processor can be reduced by replacing the general complex multipliers by constant multipliers (shift-and-add) circuits. W8 and W16 constant multipliers circuits are implemented in this thesis, which can replace three complex multipliers in the FFT processor. Finally, the FFT processors and constant multiplier circuits are implemented on Virtex-7 FPGA.
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