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Real time digital alarm clock with microprogrammed control unit

机译:带有微程序控制单元的实时数字闹钟

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摘要

Digital system design based on Field Programmable Logic Array (FPGA) is a method of choice for digital product development as it provides faster time to realize. Design software such as Xilinx ISE allows the designer to design and implement a new system on FPGA chip. Behavior of FPGA which can be defined by using VHDL provides powerful high-level constructs for describing complex logic and supports modular design methodology. Real Time Digital Alarm Clock with implementation of microprogrammed control unit is developed in this project. It is one of digital design that uses VHDL as source code and microprogrammed control unit instead of hardwired one with downloading capability to FPGA based Spartan-3 Development Board. Clocked sequential state machines are normally designed using one of two general approaches: the traditional gate and flip-flop approach or microprogramming. The microprogrammed approach to implementing control state machine has been widely used since the early 1960s and has the advantages of structured programming and fixed timing characteristics. This changed around 1990 with the widespread use of hardware description languages such as VHDL. One of the reasons for the popularity of microprogramming is that it translates the hardware design problem into a programming problem, making it tractable to a wider range of designers. Control information is stored in the microprogram memory and a new microinstruction is fetched from memory at every clock cycle. Since program changes only require a change in memory contents, the rate at which the controller can be clocked does not change, no matter how significant the program change. This is in contrast to the traditional gate and flipflop approach where changes can drastically impact the logic equations, number of gates, and clock frequency.
机译:基于现场可编程逻辑阵列(FPGA)的数字系统设计是数字产品开发的一种选择方法,因为它提供了更快的实现时间。诸如Xilinx ISE之类的设计软件允许设计人员在FPGA芯片上设计和实现新系统。可以通过使用VHDL定义的FPGA行为提供了用于描述复杂逻辑的强大高级构造,并支持模块化设计方法。该项目开发了带有微程序控制单元的实时数字闹钟。它是使用VHDL作为源代码和微程序控制单元的数字设计之一,而不是将具有下载功能的硬连线设计下载到基于FPGA的Spartan-3开发板上。时钟顺序状态机通常使用两种通用方法之一进行设计:传统的门和触发器方法或微编程。自1960年代初以来,用于实现控制状态机的微编程方法已得到广泛使用,并且具有结构化编程和固定定时特性的优点。随着硬件描述语言(例如VHDL)的广泛使用,这种情况在1990年左右发生了变化。微编程之所以受欢迎的原因之一是,它将硬件设计问题转化为编程问题,从而使其对更广泛的设计人员来说易于处理。控制信息存储在微程序存储器中,并在每个时钟周期从存储器中获取新的微指令。由于程序更改仅需要更改存储器内容,因此无论程序更改有多重要,控制器的时钟速率都不会改变。这与传统的门和触发器方法相反,在传统的门和触发器方法中,更改会极大地影响逻辑方程式,门数量和时钟频率。

著录项

  • 作者

    Md. Hamzah Mohd. Haidar;

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  • 年度 2010
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  • 原文格式 PDF
  • 正文语种 en
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