Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies

摘要

Broadband Wireless Access technologies have significant market potential, especially theudWiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for highudperformance WiMAX solutions is forcing designers to seek help from multi-core processorsudthat offer competitive advantages in terms of all performance metrics, such as speed, powerudand area. Through the provision of a degree of flexibility similar to that of a DSP andudperformance and power consumption advantages approaching that of an ASIC,udcoarse-grained dynamically reconfigurable processors are proving to be strong candidatesudfor processing cores used in future high performance multi-core processor systems.udThis thesis investigates multi-core architectures with a newly emerging dynamicallyudreconfigurable processor – RICA, targeting WiMAX physical layer applications. A noveludmaster-slave multi-core architecture is proposed, using RICA processing cores. A SystemCudbased simulator, called MRPSIM, is devised to model this multi-core architecture. Thisudsimulator provides fast simulation speed and timing accuracy, offers flexible architecturaludoptions to configure the multi-core architecture, and enables the analysis and investigationudof multi-core architectures. Meanwhile a profiling-driven mapping methodology isuddeveloped to partition the WiMAX application into multiple tasks as well as schedule andudmap these tasks onto the multi-core architecture, aiming to reduce the overall systemudexecution time. Both the MRPSIM simulator and the mapping methodology are seamlesslyudintegrated with the existing RICA tool flow.udBased on the proposed master-slave multi-core architecture, a series of diverseudhomogeneous and heterogeneous multi-core solutions are designed for different fixedudWiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIMudsimulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs atudrelatively low area costs. Meanwhile a design space exploration methodology is developedudto search the design space for multi-core systems to find suitable solutions under certainudsystem constraints. Finally, laying a foundation for future multithreading exploration on theudproposed multi-core architecture, this thesis investigates the porting of a real-time operatingudsystem – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX isudimplemented on a single RICA processor with the operating system support.