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Analysis of a radio frequency class D amplifier architecture with bandpass sigma-delta modulation

机译:具有带通sigma-delta调制的射频D类放大器架构的分析

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摘要

This thesis analyzes an amplifier architecture that combines a RF class D amplifier with a bandpass sigma-delta modulator, broadening the utility of class D amplification to include signals with envelope variation. An integrated design methodology is presented that incorporates the coding efficiency and average pulse transition frequency of the encoded pulse train into classical RF class D amplifier design equations. The equations are used to predict the power efficiency of a complementary voltage switched class D amplifier design with CMOS, pHEMT, and MESFET switches. Simulated results are compared with the analysis and verify the design methodology. The power efficiency analysis shows a direct link between modulator coding efficiency and the output power of the amplifier; therefore, a modulator with high coding efficiency is desirable. It is shown that coding efficiency depends significantly on the order of the modulator loop filter as well as the carrier oversample ratio employed in the design. The variation with carrier oversample ratio is not monotonic for second and fourth order modulators, and some oversample ratios are more optimal than others. Bandpass sigma-delta modulation synthesizes a pulse train with synchronous zero-crossings, and the coding efficiency limitations of encoding a binary amplitude pulse train with constrained zero-crossings is analyzed. The analysis and characterization of other encoder designs shows that bandpass sigma-delta modulation is remarkably efficient. The analysis is extended to pulse train upconversion employing Manchester encoding. Upconversion reduces the difficulty of implementing highly selective noise shaping resonators at RF frequencies, and the impact of upconversion in terms of coding efficiency and average transition frequency is shown.
机译:本文分析了一种放大器架构,该架构将RF类D放大器与带通sigma-delta调制器相结合,从而扩大了D类放大的效用,以包括具有包络变化的信号。提出了一种集成设计方法,该方法将编码效率和已编码脉冲序列的平均脉冲跃迁频率合并到经典的RF D类放大器设计方程中。这些方程式用于预测具有CMOS,pHEMT和MESFET开关的互补电压开关D类放大器设计的功率效率。将模拟结果与分析进行比较,并验证设计方法。功率效率分析表明调制器编码效率与放大器的输出功率之间存在直接联系;因此,期望具有高编码效率的调制器。结果表明,编码效率在很大程度上取决于调制器环路滤波器的阶数以及设计中采用的载波过采样率。对于二阶和四阶调制器,载波过采样率的变化不是单调的,并且某些过采样率比其他的最优。带通sigma-delta调制合成具有同步过零的脉冲序列,并分析了编码受过零约束的二进制幅度脉冲序列的编码效率限制。其他编码器设计的分析和特性表明,带通sigma-delta调制非常有效。该分析扩展到采用曼彻斯特编码的脉冲序列上变频。上变频降低了在RF频率上实现高选择性噪声整形谐振器的难度,并且显示了上变频对编码效率和平均转换频率的影响。

著录项

  • 作者

    Johnson Thomas Edward;

  • 作者单位
  • 年度 2006
  • 总页数
  • 原文格式 PDF
  • 正文语种 English
  • 中图分类

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