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Dynamic reconfiguration technologies based on FPGA in software defined radio system

机译:软件无线电系统中基于FPGA的动态重配置技术

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摘要

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.
机译:部分重配置(PR)是一种用于现场可编程门阵列(FPGA)设计的方法,该方法允许多个应用程序分时使用FPGA的一部分,而器件的其余部分继续不受影响地运行。使用这种策略,软件定义无线电(SDR)系统中的物理层处理体系结构可以从降低的复杂性和提高的设计灵活性中受益,因为可以将不同的波形应用程序分组为单个FPGA的一部分。波形切换通常不仅意味着更改功能,而且还意味着更改FPGA时钟频率。但是,这超出了PR处理的当前功能,因为时钟组件(例如数字时钟管理器(DCM))已从部分重新配置过程中排除。在本文中,我们提出了一种新颖的体系结构,该体系结构结合了另一种可重新配置的技术,即动态可重新配置端口(DRP)和基于单个FPGA的PR,以便动态更改功能和时钟频率。与标准的静态FPGA设计相比,该架构可显着降低硬件利用率。

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