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CPCIe:A Compression-enabled PCIe Core for Energy and Performance Optimization

机译:CPCIe:具有压缩功能的PCIe内核,可实现能源和性能优化

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摘要

PCIe is a hardware interface used in highperforming applications to move data from a central host and memory system to an accelerator such as a GPU or FPGA. In many memory bound applications, PCIe represents a bottleneck which limits the possible acceleration. In this paper, an opensource PCIe core is extended with a transparent layer of hardware compression/decompression with low latency and high throughput. The compressor/decompressor hardware operates on data values that match the width of the hardware interface and can be scaled up to higher parallelism. The results show an energy reduction of up to 84% in the PCIe transfers and up to 20% in the whole processing chain, thanks to the reduction in the number of bits that need to be moved over the power hungry wires that connect the main memory system to the accelerator in both directions. The overhead in terms of latency is maintained to a minimum and user selectable depending on the tolerances of the intended application.
机译:PCIe是在高性能应用程序中使用的硬件接口,用于将数据从中央主机和内存系统移动到加速器(例如GPU或FPGA)。在许多内存绑定应用程序中,PCIe代表了一个瓶颈,限制了可能的加速。在本文中,开源PCIe核心扩展了透明的硬件压缩/解压缩层,具有低延迟和高吞吐量。压缩器/解压缩器硬件在与硬件接口的宽度匹配的数据值上运行,并且可以按比例放大以实现更高的并行度。结果表明,由于减少了通过连接主存储器的耗电线路所需要移动的位数,PCIe传输中的能耗降低了84%,整个处理链中的能耗降低了20%系统双向加速器。延迟方面的开销可保持在最低水平,用户可以根据预期应用程序的容忍度进行选择。

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