The pipelined HIP processor in FPGA with the debugging environment

摘要

This thesis describes the implementation of a central processing unit withudpipeline called Hypothetical processor (HIP), which is described in book [1].udIt contains logic for data forwarding, an adder for floating point numbers andudit has an instruction and data cache. Through the debug unit it is possible toudread from and write to all general and to other registers in the HIPudpipeline and therefore monitor the flow of the compiled program. HIP runs in theudFPGA chip on the Spartan 3E development board where supporting logic forudmonitoring is present. The external program written in Java runs on differentudoperating systems. The monitoring program contains a text editor where it isudpossible to write in the assembler language. It also contains a compiler whichudtranslates an assembler code to HIP machine code. Operations and data areudsent to the debug unit to HIP. Each clock cycle, the monitoring program readsudthe content of every register in the CPU. The content of the main memory andudcache is seen too.