Silicon implementation of iterative detection and decoding for multi-antenna receivers

摘要

Spatial multiplexing multiple-input multiple-output (MIMO) transmission schemes are increasingly used in wireless communication systems to cope with the growing data rate requirements and at the same time improve spectral efficiency, which quantifies how effectively the available bandwidth is exploited. MIMO techniques have a relevant impact on the complexity of the baseband signal processing algorithms, which typically hinders the implementation of a receiver with near-optimal communication performance. In particular, iterating over MIMO detection and channel decoding enables relevant performance gains but presents severe hardware implementation challenges, which are the main subject of this thesis and are addressed in two steps.First, the feasibility of max-log optimal soft-input soft-output MIMO detection is proven by implementing it in silicon. The corresponding design is based on a tree search-based algorithm known as sphere decoding (SD), whose complexity scales with the signal-to-noise ratio (SNR). This property is reflected by the hardware implementation, which shows high area and energy efficiency figures at high SNRs and is nevertheless able to attain max-log optimal communication performance at low SNRs, at a decreased efficiency. The prototype presented in this thesis is the first implementation of a 4x4 MIMO detector capable of max-log maximum a posteriori (MAP) performance reported in the literature.Based on this first achievement, the second step targets the realisation of an integrated iterative detection and decoding (IDD) baseband receiver. The design presented in this thesis includes five instances of the aforementioned SD-based MIMO detector. These instances are integrated in a multicore architecture that can process up to one MIMO symbol vector per cycle, thanks to an optimised data dispatching and collecting scheme and to a specialised memory architecture. An IEEE 802.11n compliant low-density parity check (LDPC) decoder subsequently performs channel decoding to correct the errors due to the noisy channel. According to the IDD principle, the detector and the decoder iteratively exchange information about the received bits to improve the decoding result. To enable this data exchange and achieve high throughput, a shared memory is designed which allows the two processing elements to work independently, in a pipeline-interleaved fashion, on two different sets of data. Several mechanisms are integrated in the receiver to reduce the computational burden by avoiding unnecessary computations that can occur in an iterative system. At a small implementation overhead, these techniques can significantly increase the efficiency of the MIMO IDD receiver.The design was fabricated as a 65 nm CMOS prototype, the first of its kind presented in the literature. Post-fabrication measurements show that the implementation, which has a core area of 2.78 mm2, can achieve throughput figures well above 1 Gigabit/sec with an energy consumption under 1 nJ/bit in good channel conditions. At the same time, it can approach max-log MAP optimal performance at low SNR, at an increased energy cost.This tradeoff between communication performance and area/energy efficiency is key in mobile wireless devices, which have to support high data rates while providing an acceptable battery lifetime. The implications of these conflicting goals are analysed extensively in the thesis, based on the post-fabrication measurements. Such an analysis shows how the many configurable parameters of the receiver (e.g., the runtime constraints on the detector and the decoder) and of the overall communication system (e.g., the modulation, the code rate, the number of MIMO streams) can be chosen to optimise a given target, such as spectral efficiency, data rate and energy efficiency. The choice of the parameter set can significantly change depending on the optimisation goal: for instance, energy efficiency benefits from using low modulation orders, due to the reduced detection complexity, in contrast with spectral efficiency, which increases with the modulation order.The reference implementation results of the MIMO IDD receiver prototype are also used to estimate with good reliability the area and energy costs for a max-log MAP receiver as a function of the bandwidth that it has to support. The outcome of this evaluation shows that near-optimal iterative detection and decoding is not only feasible but also profitably applicable to current mobile MIMO devices and communication standards. At a small impact on the battery lifetime, this technique improves the minimum operating SNR by 1 to 2 dB, depending on the modulation scheme and code rate.