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A Reconfigurable Pattern Matching Hardware Implementation Using On-Chip Ram-Based FSM

机译:基于片内基于Ram的FSM的可重配置模式匹配硬件实现

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摘要

The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SOC) designs. Such domain-special cores are being used for their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with on-chip memory and embedded processor blocks has further extended the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. A dynamically reconfigurable Finite State Machine (FSM) can be implemented using on-chip memory and an embedded processor. Since FSMs are the vital part of sequential hardware designs, the reconfiguration can be achieved in all designs containing FSMs.In this thesis, a FSM-based reconfigurable hardware implementation is presented. The embedded soft-core processor is used for orchestrating the run-time reconfiguration. The FSM is implemented using an on-chip memory. The hardware can be reconfigured on-the-fly by only altering the memory content. The use of a processor for reconfiguration enables SOC designers to utilize both software and hardware capability to achieve reconfiguration. This scheme of reconfigurable hardware implementation is independent of the placement and routing of the hardware on the FPGA. To demonstrate the feasibility of the proposed approach, the Knuth-Morris-Pratt (KMP) algorithm was implemented. A unique way of using memory-based FSM to reconfigure and speed up the KMP search algorithm has been introduced. With the proposed technique, the system can reconfigure itself based on a new incoming pattern and perform a pattern search on a given text without involving a host processor.Data extracted from test cases shows that the proposed approach made the maximum achievable frequency of the design independent of the pattern length. The number of clock cycles required to match the pattern in the worst case is equal to the pattern length plus the text length (O (m+n)).
机译:可合成的可重新配置IP核的使用已越来越成为片上系统(SOC)设计的趋势。这样的领域专用核心因其灵活性和强大功能而被使用。配备了片上存储器和嵌入式处理器模块的多功能平台FPGA的市场引入进一步扩展了利用动态重新配置来提高整体系统适应性以满足各种产品要求的可能性。可以使用片上存储器和嵌入式处理器来实现动态可重新配置的有限状态机(FSM)。由于FSM是顺序硬件设计的重要组成部分,因此在所有包含FSM的设计中都可以实现重配置。本文提出了一种基于FSM的可重配置硬件实现。嵌入式软核处理器用于编排运行时重新配置。 FSM使用片上存储器实现。只需更改内存内容即可即时配置硬件。通过使用处理器进行重新配置,SOC设计人员可以利用软件和硬件功能来实现重新配置。这种可重配置硬件实现方案与FPGA上硬件的放置和布线无关。为了证明所提出方法的可行性,实施了Knuth-Morris-Pratt(KMP)算法。引入了使用基于内存的FSM重新配置和加快KMP搜索算法的独特方法。利用所提出的技术,系统可以基于新的传入模式重新配置自身,并在不涉及主机处理器的情况下对给定的文本执行模式搜索。从测试案例中提取的数据表明,所提出的方法使设计的最大可实现频率独立于图案长度。在最坏的情况下,与模式匹配所需的时钟周期数等于模式长度加上文本长度(O(m + n))。

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    Gauba Indrawati;

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  • 年度 2010
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