This PhD Thesis proposes new and effective approaches to reduce and estímate the powerudconsumption in processor-based architectures. This work targets embedded systems, inorderudand out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designadudto reduce or estimate the power consumption while keeping the performance constraintsudof the application and allowing the porting to other processor architectures without audhard effort by the designenudIn this context, a first work was the design of a cache power estimation tool (called IN^udCAPE), which works in parallel with the processor simulator. The power estimation utihtyudbases its results on an analytical power model, which has been fed with the expHcit calculationudof the statistical switching activity.udAfter that, reducing the power consumption in the register file of the processor architectureudwas the goal of the research. Given that the register file is one of the most power-hungryuddevices, firstly an efficient hardware mechanism to tum the unused registers of the registerudfile into a low power state has been described. A DVS technique is used to keep the Informationudstored in the registers while reducing the power consumption to a mínimum. Thisudhardware technique has been compared to an approach based on a power-aware compiler,udwhich modifies the register assignment to improve the results obtained with the banking ofudthe register file, as well as to reduce the number of required ports.udOut-of-order architectures have also been addressed, with a higher degree of complexity.udFor these systems, compiler and hardware approaches have also been proposed to efficientlyudreduce the power consumption of the register file.udFinally, MPSoCs are also the new paradigm of high-performance microprocessor design,udwhere the power dissipation becomes an even more dramatic problem. These architecturesudpresent complex design issues where the power-performance trade-off has to be carefullyudanalyzed in order to bring efficient designs. The work presented in this Ph. D. aims atudovercoming the limitation of theoretical and highly abstract models, unable to target the This PhD Thesis proposes new and effective approaches to reduce and estímate the powerudconsumption in processor-based architectures. This work targets embedded systems, inorderudand out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designadudto reduce or estimate the power consumption while keeping the performance constraintsudof the application and allowing the porting to other processor architectures without audhard effort by the designenudIn this context, a first work was the design of a cache power estimation tool (called IN^udCAPE), which works in parallel with the processor simulator. The power estimation utihtyudbases its results on an analytical power model, which has been fed with the expHcit calculationudof the statistical switching activity.udAfter that, reducing the power consumption in the register file of the processor architectureudwas the goal of the research. Given that the register file is one of the most power-hungryuddevices, firstly an efficient hardware mechanism to tum the unused registers of the registerudfile into a low power state has been described. A DVS technique is used to keep the Informationudstored in the registers while reducing the power consumption to a mínimum. Thisudhardware technique has been compared to an approach based on a power-aware compiler,udwhich modifies the register assignment to improve the results obtained with the banking ofudthe register file, as well as to reduce the number of required ports.udOut-of-order architectures have also been addressed, with a higher degree of complexity.udFor these systems, compiler and hardware approaches have also been proposed to efficientlyudreduce the power consumption of the register file.udFinally, MPSoCs are also the new paradigm of high-performance microprocessor design,udwhere the power dissipation becomes an even more dramatic problem. These architecturesudpresent complex design issues where the power-performance trade-off has to be carefullyudanalyzed in order to bring efficient designs. The work presented in this Ph. D. aims atudovercoming the limitation of theoretical and highly abstract models, unable to target the desired functional simulation and power estimation. This work also presents interestingudresults in terms of dynamic power management, voltage/frequency scaling and design spaceudexploration in MPSoCs.
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