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Analytical Computation of the Area of Pinched Hysteresis Loops of Ideal Mem-Elements

机译:理想记忆元件捏滞回线面积的解析计算

摘要

The memory elements, memristor being the best known of them, driven by a periodical waveform exhibit the well-known pinched hysteresis loops. The hysteresis is caused by a memory effect which results in a nonzero area closed within the loop. This paper presents an analytical formula for the loop area. This formula is then applied to memory elements whose parameter-vs.-state maps are modeled in the polynomial form. The TiO2 memristor, a special subset of the above elements, is analyzed as a demonstration example.
机译:由周期波形驱动的记忆元件(其中最著名的是忆阻器)表现出众所周知的收缩磁滞回线。磁滞是由记忆效应引起的,该记忆效应导致回路内闭合的非零区域。本文提出了环路面积的解析公式。然后将该公式应用于其参数与状态映射以多项式形式建模的存储元素。以TiO2忆阻器(上述元素的特殊子集)为例进行了分析。

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