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A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

机译:面向智能相机芯片3D集成的分层视觉处理架构

摘要

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15 μm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips. © 2013 Elsevier B.V. All rights reserved.
机译:本文介绍了一种视觉处理架构,该架构可直接映射到3D芯片集成技术上。由于视觉刺激中包含的信息的聚合性质,适应的体系结构比常规处理方案更有效。考虑到孤立像素值的重要性相对较小,因此在进行任何处理之前将其每个像素转换为数字是无效的。取而代之的是,我们的系统依靠焦平面图像过滤和关键点检测来进行特征提取。现在,表示图像的原始大量数据被减少为更少的抽象实体,从而简化了后续数字处理器的操作。这种分层方案的实现存在某些限制。在平面技术中并入靠近光敏器件的处理元件会对填充系数,像素间距和图像尺寸产生负面影响。因此,它影响图像传感器的灵敏度和空间分辨率。基本的权衡需要解决。传送到传感器平面的处理量越大,像素间距越大。相反,使用较小的像素间距会将更多的处理电路发送到传感器的外围,并拉紧传感器平面和存储平面之间的数据瓶颈。具有高硅通孔密度的3D集成技术可以帮助克服这些限制。传感器平面与处理和内存平面的垂直集成以及完全并行的连接消除了数据瓶颈,同时又不影响填充系数和像素间距。提出了一个案例研究:基于MIT Lincoln Labs提供的3D集成技术设计的智能视觉芯片,其基本工艺为0.15μmFD-SOI。与智能视觉芯片的最新技术相比,仿真结果可提高性能。 ©2013 Elsevier B.V.保留所有权利。

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