Design, Fabrication and Characterization of Tunnel Field Effect Transistors for Ultra-Low Power CMOS Applications

摘要

Silicon CMOS has emerged over the last 25 years as the predominant technology of the microelectronics industry. The concept of device scaling has been consistently applied over many technology generations, resulting in consistent improvement in both device density and performance. In the last decade, the shrinking of the transistor dimensions led to short channel effects (SCEs) which decreases the device performance. As a consequence, additional improvements were needed to maintain the performance improvements such as the introduction of SiGe S/D stressors to increase the carrier mobility due to the strain in the channel, the implementation of high-K and metal gate to reduce the gate leakage and, finally, the introduction of a new 3D architecture, finFET, to further suppress the SCEs. On the other hand, no solutions exist for the scaling of the dissipated power of the transistor. In fact, the scaling of the supply voltage (Vdd) is limited by the kT/q limit of the subthreshold slope which represents a physical limit for conventional MOSFETs. As a consequence, a new operation principle is needed.In this context, the Tunnel FET (TFET) has been proposed as a potential candidate to replace the MOSFET because its carrier injection mechanism based on quantum mechanical tunneling of the electrons from valence band to the conduction band and it is not subjected to the kT/q limit. The basic embodiment of TFET is a gated p-i-n diode. This thesis addresses the design, fabrication and characterization of TFETs following a CMOS compatible processing flow. The main goal is to understand the features of band to band tunneling from an experimental point of view and identify the best processing conditions and the best architecture for TFETs. The analysis starts from silicon homojunction gated p-i-n diodes to heterojunction devices where the source is replaced with SiGe with different germanium concentrations. Two different architectures are studied: finFETs and vertical nanowires. The finFETs are used as a test vehicle to study Si TFETs since the finFET processing is already mature. On the other hand, the vertical architecture is used to implement hetero junction TFET. Finally, in view of the limitations for the basic TFET embodiments, a new architecture to boost the on current of TFETs is proposed and analyzed by TCAD simulations.