Optical communications is expanding into new applications such as infrared wirelesscommunications; therefore, designing high performance circuits has gained considerableimportance. In this dissertation a wide dynamic-range variable-gain transimpedance amplifier(TIA) is introduced. It adopts a regulated cascode (RGC) amplifier and an operationaltransconductance amplifier (OTA) as the feed forward gain element to control gain and improvethe overload of the optical receiver. A fully-differential variable-gain TIA in a 0.35?m CMOStechnology is realized. It provides a bit error rate (BER) less than 10-12 for an input current from6?A-3mA at 3.3V power supply. For the transimpedance gain variation, from 0.1k?? to 3k??,-3dB bandwidth is higher than 1.7GHz for a 0.6pF photodiode capacitance. The powerdissipations for the highest and the lowest gains are 8.2mW and 24.9mW respectively.A new technique for designing uniform multistage amplifiers (MA) for high frequencyapplications is introduced. The proposed method uses the multi-peak bandwidth enhancementtechnique while it employs identical, simple and inductorless stages. It has several advantages,such as tunability of bandwidth and decreased sensitivity of amplifier stages, to processvariations. While all stages of the proposed MA topology are identical, the gain-bandwidthproduct can be extended several times. Two six-stage amplifiers in a TSMC 0.35?m CMOSprocess were designed using the proposed topology. Measurements show that the gain can be varied for the first one between 16dB and 44dB within the 0.7-3.2GHz bandwidth and for thesecond one between 13dB and 44dB within a 1.9-3.7GHz bandwidth with less than 5.2nV/?Hznoise. Although the second amplifier has a higher gain bandwidth product, it consumes morepower and occupies a wider area.A technique for capacitance multiplication is utilized to design a tunable loop filter.Current and voltage mode techniques are combined to increase the multiplication factor (M). Ata high input dynamic range, M is adjustable and the capacitance multiplier performs linearly athigh frequencies. Drain-source voltages of paired transistors are equalized to improve matchingin the current mirrors. Measurement of a prototype loop filter IC in a 0.5?m CMOS technologyshows 50?A current consumption for M=50. Where 80pF capacitance is employed, thecapacitance multiplier realizes an effective capacitance varying from 1.22nF up to 8.5nF.
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