Compact fluorescent and solid-state lights rapidly gain ground in the lighting market. Developments in the size, efficiency and reliability of these light sources are accompanied by advancements in the embedded electronics driving them. The long lifetime of these light sources requires that the electronics parts last at least equally long. The power transistor, a transistor specially designed to withstand high voltages or currents, is a key component in these and many other (e.g. automotive) electronics. This PhD-work focuses on the development of optimization methodologies for these power transistors and studies how long-term electrical stress affects their performance. The developed (gradient based) optimized device designs result in smaller and therefore less expensive transistors with an almost constant internal electric field (Reduced SURface Field - RESURF) having many unique features useful for modeling and the prediction of electrical behavior. During electrical stress however, parasitic charge can build up in certain locations, thus distorting the electric field distribution which in turn leads to changing (potentially destructive) transistor performance. The main mechanisms responsible for degradation in these transistors under different stress conditions are identified, as well as the location in the transistor where the stress induced physical and chemical changes take place. Diagnostic techniques and analytical models were subsequently developed to allow the prediction of the transistor’s performance after stress. As such, this work provides the necessary insights and tools for the design and in depth electrical characterization of gradient based field-plate assisted RESURF optimized power transistors before and after electrical stress.
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