Active Paralleling of High Power Voltage Source Inverters

摘要

Power electronics are becoming established in ever broadening areas of industry. The transition from previous generation technology is driven by the oportunity for improvements in controllability, efficiency, and longevity. A wide variety of power semiconductors are available, however power handling capacity is still a significant limitation for many applications. An increase in the capacity of a single device is usually accompanied by a drop in switching frequency, and hence achievable system bandwidth. Increased capacity can be attained without this loss in bandwidth by using multiple lower power devices in parallel. Products based on parallel device topologies are already present in the marketplace, however there are many associated complications. The nature of these complications depends on the control method and topology used, but no system combines high performance and high power with high reliability and easy maintainability. This research aims to identify and develop a method that would provide a system of voltage source inverters with a total capacity in excess of 10MVA, with effective control bandwidth comparable to a 100kVA system. Additionally, the method should be equally applicable at still higher power levels in the future with the anticipated development of higher capacity power semiconductors. The primary goal when using paralleled devices is to achieve an even distribution of system load between them, as unbalanced load leads to poor system utilisation. Devices can be paralleled either passively, in which devices are controlled in common and characteristics inherent to the device are relied upon to balance load; or actively, in which devices are individually controlled and monitored to improve load balance. A key component of the thesis is the identification and analysis of the inadequacies inherent to passively paralleled systems. It is the limitations of passive paralleling that provide the motivation to develop an active parallel control mechanism. Following the analysis, an active control algorithm is developed and implemented on a paralleled system. The proposed system topology consists of an array of medium power Voltage Source Inverter (VSI) modules operating in parallel. Each module is controlled semi-independently at a local level, with an inter-module communications network to enable active equalisation of module load, and redundant fault management. An innovative load equalisatiion algorithm is developed and proven, the key feature of which is this inclusion of a synthetic differential resistance between modules within the system. The result is a modular expandable structure offering the potential for very high power capacity combined with quality of response usually only found in low power systems. The system as a whole is extremely reliable as any module can be isolated in the event of a fault without significantly affecting the remainder of the network. Performance results from both simulation and experimentation on a two module small scale prototype are given. Using the developed topology and control method extremely accurate load balancing can be achieved without degradation of the response characteristics. The system is tested up to only 2.4kW in the course of this research, but the correlation with simulation is high and gives confidence that the developed mechanism will allow the 10MV A goal to be achieved. Following the developmental stage of this research the technology has been applied to a commercial system comprising parallel structures of up to 8 modules with a total power handling capacity of 1MVA with no deterioration in performance. 2MVA systems are deliverable with the current technology without any changes, and higher power levels are expected to be easily achieved.