Validation Support for Distributed Real-Time Embedded Systems in VDM++:Technical rept. series

摘要

We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system architects with rapid feedback on the timing characteristics of alternative designs in the often volatile early stages of the development cycle. The approach extends the Vienna Development Method (VDM++), a formal object-oriented modeling language with facilities for describing real-time applications deployed over a distributed infrastructure. A new facility is proposed for stating and checking validation conjectures (assertions concerning real-time properties) against traces derived from the execution of scenarios on VDM++ models. We define validation conjectures and outline their semantics. We describe the implementation of conjectures against execution traces as a formally-defined extension to the existing VDM++ tool set, and show tools to support the visualisation of traces and validation conjecture violations. The approach and tool support are illustrated with a case study based on an in-car radio and navigation system.